1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly relates to a semiconductor memory device fit to mixture with logical processing circuit units such as MPU (Microprocessor), CPU (Central Processing Unit), ASIC (Application Specific Integrated Circuit) and the like, as well as a logic contained semiconductor memory device or a memory contained logical processing circuit unit in which a logical processing circuit unit and a semiconductor memory device are mixed.
2. Description of the Background Art
FIG. 39 schematically shows an entire arrangement of a processor containing DRAM (Dynamic Random Access Memory) in which a conventional DRAM and a processor are formed on the same chip. Referring to FIG. 39, the conventional processor containing DRAM is integrated on a semiconductor chip 900. The microprocessor containing DRAM includes DRAM arrays 902a, 902b, 902c and 902d respectively arranged in four regions #A, #B, #C and #D on semiconductor chip 900. Each of DRAM arrays 902a-902d includes dynamic memory cells arranged in rows and columns.
Corresponding to respective DRAM arrays 902a-902d, row decoders 903a, 903b, 903c and 903d each for selecting a row in a corresponding DRAM array, column decoders 904a, 904b, 904c and 904d each for selecting a column in a corresponding memory array, and preamplifier.write driver blocks 905a, 905b, 905c and 905d each for writing/reading of data into/from a corresponding DRAM array are provided. Preamplifier.write driver blocks 905a-905d are respectively coupled with internal read/write data buses 907a, 907b, 907c and 907d each having a width of 32 bits to 256 bits.
In a region #E between regions #A and #B and regions #C and #D, a processor (CPU) 920 which supplies and receives necessary data to and from DRAM arrays 902a-902d and executes various processings as well as a DRAM control circuit 910 which controls an access to DRAM arrays 902a-902d according to a command from processor 920 are provided.
DRAM control circuit 910 generates and sends via an internal bus 912a a control signal for controlling activation/inactivation of row decoders 903a and 903b, column decoders 904a and 904b and preamplifier.write driver blocks 905a and 905b, and an address signal for selecting a row and a column. Control circuit 910 also supplies a control signal and an address signal via an internal bus 912b to row decoders 903c and 903d, column decoders 904c and 904d, and preamplifer.write driver blocks 905c and 905d. Internal bus 912b is arranged to extend from DRAM control circuit 910 to regions #C and #D across processor 920.
Processor 920 is coupled with internal read/write data buses 907a, 907b, 907c and 907d and inputs/outputs necessary data. Internal read/write data buses 907a and 907b is coupled with processor 920 across DRAM control circuit 910.
In this processor containing DRAM, DRAM arrays 902a-902d are simultaneously driven into an active state, and data are transferred between DRAM arrays 902a-902d and processor 920 via internal read/write data buses 907a-907d. Since internal read/write data buses 907a-907d each has a sufficiently large width of, for example, 32 bits to 256 bits, data of 128 bits to 1024 bits can be transferred in one transfer cycle and a band width for data transfer can be increased. If the DRAM and the processor are discretely provided, the operating speed of the DRAM cannot follow the operating speed of the processor and high speed data transfer becomes impossible accordingly, and the operating speed of the DRAM becomes a bottleneck against processing performance of the processor. The processor containing DRAM described above aims to solve such a problem.
Particularly by integrating processor 920 and DRAM arrays 902a-902d on the same semiconductor chip 900, the bit width of internal read/write data buses 907a-907d can be increased sufficiently without limitation by external pin terminals. Further, by integrating DRAM arrays 902a-902d and processor 920 on semiconductor chip 900, interconnection line capacitance and resistance of internal read/write data buses 907a-907d can be reduced relative to those of interconnection lines on a circuit board. As a result, data can be transferred at high speed.
The processor containing DRAM shown in FIG. 39 has a single bank configuration in which DRAM arrays 902a-902d are all simultaneously activated/inactivated. Considering localization of data to which the processor makes access, a multi-bank configuration containing a plurality of banks is preferable for a high speed operation. In this case, during an access to one bank, another bank is driven from an inactive state to an active state in order to prepare for an access by the processor. Following completion of the access to the one bank, an access is made to this another bank. In the single bank configuration, RAS precharge time is necessary for activating DRAM arrays 902a-902d after precharging of the DRAM array in order to obtain necessary data again. In the multi-bank configuration, such RAS precharge time is not required and a high speed access is implemented. However, a processor containing the multi-bank DRAM has not been proposed.
The bus width of internal read/write data buses 907a-907d should be further increased in order to modify DRAM arrays 902a-902d of FIG. 39 into the multi-bank configuration. In a two-bank configuration, for example, one bank is constituted of two memory arrays. In this case, data can be only transferred simultaneously between processor 920 and two DRAM arrays. In order to implement a data transfer band width which is equal to that of the single bank configuration, the width of internal read/write data buses should be doubled. Since the doubled width of the buses increases the area occupied by interconnection lines, an efficient layout of internal circuits is required for avoiding increase of the chip area. However, such an efficient layout for preventing increase of the chip area in the multi-bank DRAM has not been proposed.
In addition, in the processor containing DRAM shown in FIG. 39, the length of internal bus 912a and that of internal bus 912b differ from each other, resulting in different signal propagation delays. The difference of the length of internal buses 912a and 912b is canceled by the difference of the length of internal read/write data buses 907a and 907b and that of buses 907c and 907d so as to obtain the same access time. However, difference of delay time in internal read/write data buses 907a-907d and difference of delay time in internal buses 912a and 912b cannot be made precisely equal to each other due to difference of parasitic capacitance of the interconnection lines or the like. Therefore, some margin is required for data access. Further, since timings of starting/stopping of internal access of the banks and timings of activating/inactivating the arrays are different, collision of data could occur when the banks are accessed in the interleaved manner.
In this case, if DRAM arrays 902a and 902b constitute one bank and DRAM arrays 902c and 902d constitute the other bank in FIG. 39, access times of those banks are different from each other and the access time is determined according to the worst case, so that a high speed access cannot be implemented. If DRAM arrays 902a and 902c constitute one bank, data access time of DRAM array 902a is different from that of DRAM array 902c. In this case, the access time is also determined according to the worst case, so that a high speed access cannot be implemented.
In the case of such a processor containing DRAM or a circuit unit in which logic and DRAM are mixed, the processor or unit is often designed on a cell base (because automatic design is used). The processor or unit is hierarchically designed utilizing the DRAM as a macro (functional block). However, a multi-bank DRAM macro having an efficient layout which is fit to mixture with a processor or logic, enables a high speed access and does not increase the occupied area has not been prepared yet.